Embedded world RISC-V International has expanded its stack of open, royalty-free specifications, with additional documents covering firmware, hypervisors, and more.
RISC-V – pronounced “risk five”, and not to be confused with the other architecture of this name, RISC-5 – basically defines how a processor core works from a software perspective. Chip designers can implement these instruction set specifications in silicon, and there are a good number of big players in the industry support this.
The last specifications expose four features that compatible processors must adhere to. Two of them, E-Trace and Zmmul, will be useful to organizations creating RISC-V hardware and software, and the other two may prove important in the future, aiding in the development of working operating systems. on RISC-V computers.
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One of them is the UEFI Boot Protocol which specifies how the system firmware obtains and manages hardware information before loading an operating system kernel. Another defines a Supervisor binary interface (SBI) between hardware and an operating system or hypervisor kernel, with a reference implementation by Western Digital called OpenSBI.
Mark Himelstein, CTO of RISC-V International, said it was an “essential resource”, providing “the ability to port software in supervisor mode to all RISC-V implementations, essentially allowing developers to write something once and apply it everywhere”.
As with the others, the E-Trace specification enables efficient processor branch tracing on RISC-V devices. If that’s your kind of jam, there’s a 100+ page PDF on GitHub.
The Zmmul extension specifies support for multiplication, non-division math, primarily for small and simple embedded cores – there are already separate extensions for integer and floating-point math, including multiplication and division, for general purpose application processor cores.
(RISC-y historical note: The original Acorn ARM1 processor had no hardware for multiplication or division, but it did have a barrel gear lever.)
The RISC-V instruction set architecture is still in its infancy and, like some The Reg have already said, its future success remains far from certain. There isn’t a lot of general-purpose end-user RISC-V hardware out there that you can buy and try out yourself, or run an emulator like Qemu.
One of the few examples is the optional RISC-V processor module for the ClockworkPi DevTerm. One of the earliest reviews of the RISC-V version can be found on former TenFourFox browser maintainer Cameron Kaiser’s blog. TalosSpaceand although he likes the device very much, the review is very negative about the performance of the machine’s single-core Allwinner system-on-chip.
For now, RISC-V poses no real threat to anyone on the performance front of high-end general-purpose processors. Apple has shown that investing a lot of time and money in building a highly integrated, large-scale Arm SoC is definitely worth it, whether in terms of raw performance, performance per watt, or price: performance . Now the rest of the Arm industry has to catch up with Apple, while RISC-V has yet to try to catch up with Arm.
That said, at the time at least, the Arm world was a Silicon Wild West with every chip different, and it took a lot of industry effort and cooperation to, in some areas, standardize things like firmware and the boot process. This is why a project like Armbian was born. Kudos to RISC-V International for realizing this and tackling it at an early stage. ®
The name RISC-V comes from the fact that it is the fifth generation of the original Berkeley RISC pattern. The RISC-I chip had 78 registers, but its performance was disappointing (see the unusually discursive Wikipedia article before someone deletes it). Nevertheless, it inspired Sun’s original SPARC processor.
RISC-II had a remarkable 138 registers. RISC-III was the ASCEND CPU (Smalltalk On A RISC), and RISC-IV the processor for SPUR (Symbolic Processing Using RISCs), a very first parallel processor workplace.